A conventional automatic gain controlled (AGC) amplifier includes a digital variable-gain amplifier that amplifies an input signal, a detector that detects the amplitude of the amplified signal provided by the amplifier, and a control circuit that compares the detected amplitude with a reference voltage and then adjusts the gain of the amplifier such that the detected amplitude does not exceed the reference voltage.
The input signal is an AC analog signal that can be provided with a DC bias. The AGC circuit makes it possible to utilize the control characteristics of an analog to digital converter in order to optimize the resolution of a digitized signal. A tolerance band is specified in which the signal amplitude should lie. The width of the tolerance band, the hysteresis zone, depends upon the shape of the analog signal. A narrower hysteresis zone can be used with a higher frequency signal. In the case of audio signals, in which the AC signal is mixed with a carrier signal, the hysteresis zone is chosen such that the automatic gain control does not respond to ordinary, short-time signal variations, which would lead to distortions.
European Patent Application EP-A-325 252 filed on Jan. 19, 1989 discloses an automatic gain control circuit with a digitally adjustable amplifier. The output of the amplifier is coupled to a peak-value sample-and-hold circuit whose analog output is evaluated by means of a window comparator. The hysteresis range of this window comparator is determined by two reference voltages each of which is applied to the reference input of one of two comparators included in the window comparator. The outputs of the two comparators are applied to a control stage which produces a digital control signal for the digitally adjustable amplifier by means of an up-down counter. Different sampling rates can be set by means of two applied clock signals.
Among the disadvantages of this prior art circuit, it is not suited for implementation in monolithic integrated MOS technology, particularly without external components. At the relatively low sampling rates, the holding of the sampled analog voltage values requires high memory capacities, which are hardly realizable in view of the amount of chip area required.
Further, this conventional circuit requires a costly and complicated peak-value sample and hold stage. The circuit employs capacitors and resistors in the peak-value sample and hold stage. The capacitors and resistors dictate the speed at which the gain is adjusted. Drivers are required to reverse charges that are stored on capacitors. Speed of adjustment is also dictated by the nature of the input signal.
Therefore, it is an object of the present invention to provide automatic gain control apparatus which is suitable for MOS integration, particularly CMOS integration, and whose holding device requires no storage capacitors.
It is a further object of the present invention to eliminate the peak-value sample and hold circuit of the prior art.